1. Field of the Invention
The present invention relates to sigma-delta digital to analog converters (DACs), and more particularly to methods and apparatuses for mismatch shaping of an oversampled converter. Even more specifically, the present invention relates to mismatch shaping networks for use in multi-bit DACs.
2. Background Art
It is known to process analog signals using digital circuitry. Typically, such circuitry converts analog signal to binary values, arithmetically manipulates the binary values with binary circuitry to perform filtering and digital signal processing, and then converts the processed binary values back into analog signals (e.g., for sound reproduction). To minimize the circuitry required to convert the analog signals to binary values, sigma-delta modulators are often utilized.
Sigma-delta modulators sample the analog signal at a rate that is orders of magnitude greater than the highest frequency present. Sigma-delta modulators use the technique of oversampling and noise shaping to move most of the quantization noise outside the band of the signal. The out of band noise may then be filtered out such that the signal to noise ratio (SNR) within the signal band is significantly increased.
The use of a multi-bit sigma-delta DAC lowers the in-band and out of band quantization noise as compared to single bit modulators with single bit DACs. However, multi-bit modulators typically require multi-bit DACs with highly linear performance. The linearity of a multi-bit DAC is typically limited by how precise analog elements, such as capacitors, resistors or current sources, can be matched. The linearity performance of analog components fabricated with standard CMOS techniques is less than 13 bits. Therefore, mismatch shaping circuitry is often utilized to improve the linearity performance of the analog components. Mismatch shaping circuitry shapes the mismatches in the analog unit elements to substantially reduce errors in the signal band of an oversampling converter.
A method and apparatus for performing dynamic element matching is disclosed in Leung, U.S. Pat. No. 5,406,283, entitled xe2x80x9cMulti-bit oversampled DAC with dynamic element matching.xe2x80x9d The Leung patent discloses a technique for cyclically selecting successive different permutations of the unit elements for converting each value of the output digital signal thereby canceling the mismatching between unit elements. However, the digital complexity of such a method increases tremendously with the number of bits in the digital output. For example, a typical implementation of such a system requires an encoder for each value of output digital signal, a memory element or pointer for each digital value and a Mxc3x97M cross-point switch, where M is the number of unit elements. Therefore, as the number of unit elements doubles the encoder and memory elements required increases by a factor of two but the cross-point switch complexity and hardware increases by a factor of four, or more generally as a square term.
In addition, there is a possibility for pattern noise to occur since the unit elements are cyclically selected. For example, if the same code is output each time and if there are mismatches on the unit elements, a spur may occur at a frequency given by the inverse of the cyclical selection period.
Therefore, it would be advantageous to provide a method and apparatus for mismatch shaping of oversampled data converters that does not suffer from the above described design complexity and pattern noise errors.
An embodiment of the present invention is directed to a method and apparatus for spectrally shaping mismatch errors in a multi-bit digital to analog converter (DAC) constructed from K separate multi-element sub-DACs, where K and the number of elements in each sub-DAC are each preferably greater than two. A received digital input code is split into a set of K sub-codes corresponding to the digital input code. The set of K sub-codes can have one of at least N different sub-code orders that specify an order of each of the K sub-codes with respect to one another, where N greater than 2. A sum of the K sub-codes equals the digital input code. One of the at least N different sub-code orders is selected using a shuffling algorithm. Then, each sub-code in the set of K sub-codes is output in accordance with the selected sub-code order.
In an embodiment of the present invention, each of the K sub-codes is not different than any of the other K-1 sub-codes within the set of K sub-codes by more than one level.
According to an embodiment of the present invention, the shuffling algorithm is a dynamic element mismatch shaping algorithm. In this embodiment, the selecting the one of the at least N different sub-code orders is performed using the dynamic element mismatch shaping algorithm.
In an embodiment of the present invention, the selecting of the one of the at least N different sub-code orders based on (1) one or more sub-code orders that were previously selected, and/or (2) a pseudo random code.
In an embodiment, each sub-code in the set of K sub-codes is provided to a respective one of K shufflers in accordance with the selected sub-code order. Each of the K sub-codes is then separately shuffled using the respective shuffler to thereby produce K separate multi-bit shuffled density codes. In an embodiment, each of the K shuffled density codes is then provided to a respective one of K multi-element sub-digital-to-analog converters (sub-DACs), in accordance with the selected sub-code order. Each of the K multi-element sub-DACs is driven using the respective one of the K shuffled density codes. A plurality of analog signals are thereby produced and combined to produce a combined analog signal representative of the received digital input signal.
According to an embodiment of the present invention, a range signal is produced based on a received digital input code. The range signal specifies which one of a plurality of ranges the digital input code is within. A density code is then produced. The density code specifies a level within the range expressed by the range signal. The producing of the density code may include selecting one of a plurality of orders for the density code using a shuffling algorithm, wherein each of the orders specify an order of bits in the density code. Preferably, as these steps are repeated, each one of the different orders, on average, is selected substantially the same number of times.
The range signal and the density code are then combined to thereby produce a plurality of sub-codes. A sum of the plurality of sub-codes equals the digital input code. Each of the plurality of sub-codes are preferably shuffled to produce a plurality of shuffled density codes. Each of the plurality of shuffled density codes is then provided to a respective multi-element sub-digital-to-analog converter (sub-DAC). The sub-DACs convert the shuffled density codes to analog signals, the sum of which equal the received digital input code from which the range and density signal were produced.
In an embodiment of the present invention, a digital input code having a first value V1 is received. A second digital value V2 is then produced, wherein V2 equals a greatest integer less than V1÷K, where K greater than 2. Additionally, a third digital value V3 is produced, where V3 equals V1 modulo K. Next, a shuffled density code is produced based on the third digital value V3. The shuffled density code includes K bits each of which has a value of 0 or 1. An order of the K bits with respect to one another is based on a shuffling algorithm. Then, V2 is separately added to each of the K bits to produce K separate further digital outputs V41 . . . V4K. A sum of the K separate further digital outputs equals the first       V1    ⁢          xe2x80x83        [                  i        .        e        .            ,                                    ∑                          i              =              1                        k                    ⁢                      xe2x80x83                    ⁢                      V4            i                          =        V1              ]    .
Each of the K separate further digital outputs V41 . . . V4K can then be provided to one of K separate shufflers. Each of the digital outputs V41 . . . V4K is then shuffled using one of the K shufflers to produce a respective shuffled density code, thereby producing K shuffled density codes for each digital input code.
Each of the K shuffled sub-codes is then provided to a separate one of K multi-bit sub-digital-to-analog converters (sub-DACs). The sub-DACs are used to convert each of the K shuffled density codes to analog signals, thereby producing a plurality of analog signals. The plurality of analog signals are then combined to produce a combined analog signal that is representative of the first value V1.